Various techniques for validation of Integrated Circuit (IC) design are known in the art. Some techniques, sometimes referred to as post-silicon validation, test the design in its hardware form. For example, Adir et al. describe techniques for post-silicon validation, targeting multi-threaded processors, in “Threadmill: a Post-Silicon Exerciser for Multi-Threaded Processors,” Proceedings of the 48th Design Automation Conference (DAC), Jun. 5-10, 2011, pages 860-865, which is incorporated herein by reference. Examples of schemes for random test generation are described by Storm, in “Random Test Generation for Microprocessor Design Validation,” Proceedings of the 8th EMICRO, May 12, 2006, which is incorporated herein by reference. Concurrent test generation is also addressed by Adir et al., in “Concurrent Generation of Concurrent Programs for Post-Silicon Validation,” IEEE Transactions on CAD of Integrated Circuits and Systems, volume 31, issue 8, 2012, which is incorporated herein by reference.
U.S. Pat. No. 7,945,888, whose disclosure is incorporated herein by reference, describes a method that includes building an executable image of a hardware exerciser adapted for execution on a test platform. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.
U.S. Pat. No. 8,516,229, whose disclosure is incorporated herein by reference, describes a test code generation technique that generates an output set of program code by replacing a particular instruction with a redirecting instruction for redirecting execution to a handling routine. When the redirection instruction is reached, the handling routine is entered. The handling routine determines a state of the processor such that a desired result of the particular instruction is selected by specifying a replacement instruction having the desired result when executed and replacing the redirection instruction with the replacement instruction. The program code is then re-executed, either immediately or on a next iteration, so that the replacement instruction generates the desired result when executed.